The development of semiconductor devices is advancing towards higher integration. The higher integration requires miniaturization of an insulated-gate field-effect transistor (hereinafter referred to as “MOS transistor”) in order to suppress increase of chip size.
A CMOS-type semiconductor device of a dual-gate structure is employed to suppress short-channel effects being caused by miniaturization of MOS transistors so as to obtain a threshold-voltage level comparable to that of conventional-type MOS transistors. The dual-gate-structure CMOS-type semiconductor device includes a p-channel-type MOS transistor (hereinafter referred to as “p-MOS transistor”). The p-MOS transistor is provided with a gate electrode of poly-silicon containing high concentration p-type impurities. Such a gate electrode is called as “p+ poly-silicon gate electrode”.
The dual-gate-structure CMOS-type semiconductor device further includes an n-channel-type MOS transistor (hereinafter, referred to as “n-MOS transistor”). The n-MOS transistor is provided with a gate electrode of a poly-silicon containing high concentration n-type impurities. Such a gate electrode is called as “n+ poly-silicon gate” electrode. These two types of MOS transistors are formed in a common semiconductor substrate.
In manufacturing the p+ and n+ poly-silicon gate electrodes, a poly-silicon film is selective etched, after high-concentration p-type and n-type impurities are doped into the respective poly-silicon areas of the poly-silicon film.
The etching is usually carried out by a reactive ion etching (RIE) method. The poly-silicon areas, which have different conductivity types, are etched at different rates by the RIE method. The difference in the etching rate causes a problem that the gate electrode of the p-MOS transistor differs in dimensions and shape from that of the n-MOS transistor.
Such a difference in dimensions and shape causes unevenness of characteristics between the p-MOS transistor and the n-MOS transistor. Accordingly, the dual-gate-structure CMOS-type semiconductor device is difficult to have constant characteristics. The, in turn, results in difficulty in miniaturization of the CMOS-type semiconductor device.
Japanese Patent Application Publication (Kokai) No. 2004-266249, for example, discloses a method of reducing the difference in dimensions and shape between the p-type and n-type gate electrodes. Such reduction is implemented by changing etching condition between low and high impurity-concentration regions of a poly-silicon film, which has been doped with p-type and n-type impurities.
The low impurity concentration region is a lower portion of the poly-silicon film. The high impurity concentration region is an upper portion of the poly-silicon film. Different etching conditions are respectively applied to the lower and upper portions.
The lower and low impurity concentration portion is etched under a first etching condition using an etching gas containing a halogen/oxygen-based gas.
Further, the upper and the high impurity concentration is etched under a second etching condition using an etching gas containing CF-based gas. Under the second etching condition, side etching is less likely to occur than under the first conditions.
With these measures, the difference is reduced in shape between the p-type and n-type gate electrodes.
Nevertheless, there still remains a problem that the p-type and n-type gate electrodes formed are different from each other in size. Thus, the gate electrodes do not always show desirable shape and dimensions.